This section contains a brief description of the LEON3 SPARC V8 processor implementation developed by Gaisler Research, with an emphasis on information. LEON3 is a synthesizable VHDL model of a bit processor compliant with the SPARC V8 architecture. The processor is highly configurable, and particularly. LEON3 Processor. SPARC V8 instruction set with V8e extensions; Advanced 7- stage pipeline; Hardware multiply, divide and MAC units; High-performance, fully .

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This article is about the family of microprocessors. Microprocessors are a core component of modern electronics and on-board computers do not escape this rule.

LEON – Wikipedia

This allows new users to quickly define a suitable custom configuration. The goals have been to detect and keon3 one error in any register without software intervention, and to suppress effects from Single Event Transient SET errors in combinational logic. The LEON4 processor has the following features: Retrieved from ” https: Airbus Defense and Space.

Up to 16 CPU can be used in a multiprocessing configuration.

LEON3 Processor – MechatronicsUSP

Debugging is generally done using the gdb debugger, and a graphical front-end such as DDD or Eclipse. The full source code is available under the GNU GPL license, allowing free and unlimited use for research and education.

Archived from the original PDF on It has been designed for operation in the harsh space environment, and includes functionality to leo3 and correct single event upset SEU errors in all on-chip RAM memories.


It features the following:. Aeroflex Gaisler – Device: Currently 5 out of 5 Stars.

It is possible to perform source-level symbolic debugging, either on a simulator or using real target hardware. The NGMP has the following on-chip functions: For industrial and high-rel applications, ports for Processpr 5.

Archived copy as title Webarchive template wayback links Articles lacking reliable references from November All articles lacking reliable references Articles containing Spanish-language text Articles with Curlie links. LEON3 is also available under a proprietary license, allowing it to be used in proprietary applications.

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Views Read Edit View history. It is highly procezsor, and was designed for embedded applications with the following features on-chip: The NGMP has the following on-chip functions:.

For other uses, see Leon disambiguation. It is highly configurable, and was designed for embedded applications with the following features on-chip:.

November Leoh3 how and when to remove this template message.

LEON3 Processor

Retrieved from ” http: Your rating has been changed, thanks for rating! BCC includes a small run-time with interrupt support and Pthreads library. You have already rated this page, you can only rate it once! A single cross-compilation tool-chain is provided which is capable of compiling the kernel and applications for any configuration.

Later processors in the LEON series are used in a wide range of designs and are therefore not as tightly coupled with a standard set of peripherals.


The model is highly configurable, and particularly suitable for system-on-a-chip SoC designs. The LEON3 template designs can be configured using a graphical tool built on tkconfig from the linux kernel.

SnapGear Linux is a full source package, containing kernel, libraries and application code for rapid development of embedded Proxessor systems. The LEON4 processor has the following features:. The fault-tolerance is provided at design VHDL level, and does not require an SEU-hard semiconductor process, nor a custom cell library or special back-end tools.

More information regarding these models can is available on the Aeroflex Gaisler website. The configuration tool not only configures the processor, prodessor also other on-chip peripherals such as memory controllers and network interfaces. LEON has a dual license model: While the LEON2 -FT design can be extended and re-used in other designs, its structure does not emphasise re-using parts of the design as building blocks or enable designers to easily incorporate new IP cores in the design.

Branch prediction, 1-cycle load latency and a 32×32 multiplier results in a performance of 1. The certification was completed on May 1, Pre-synthesized FPGA programming files are also provided. This website requires javascript to function properly.