microprocessor architecture divided in The BIU has to interact with memory and of the programs and to carry out the required processing. EU & BIU. Explanation of the purpose of EU and BIU in Bus Interface Unit (BIU): The BIU interface to outside word. It provides full 16 bit. Define the jobs performed by the BIU and EU in the The functions performed by the Bus interface unit are: The BIU is responsible for the external bus.

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Write short notes on the Execution Unit (EU) and the Bus Interface Unit (BIU).

Ibu is a process to speed up the processor. As we begin writing programs the consequences of these definitions will become clearer. An address within a segment is called an offset or logical address.

Because the next several instructions are usually in the queue, the BIU can access memory at a somewhat “leisurely” pace. This is a little “tricky” because the segment registers are only 16 bits wide, but the memory address is 20 bits wide. What are the temporary registers of the microprocessor? It receives and outputs all its an through BIU.

This is base pointer register pointing to data in stack segment. What is the full form of STD in microprocessors ? They are set using certain instructions.

Execution Unit (EU):

The CS register contains the segment number of the next instruction and the IP contains the offset. Depending on the execution time of the first instruction, the BIU may fill the queue with several new instructions before the EU is ready to draw its next instruction.


Execution unit gives instructions to BIU stating from where to fetch the data and then decode and execute those instructions. The logical address is an offset from location 0 of niu given segment. It is used for addressing a memory location in the code segment of the memory, where the executable program is stored. Functional Block Diagram of Microprocessor. Another way if saying this is that the low-order hex digit must be 0. Control flags controls the operations of the execution unit.

Addresses within a segment can range from address h to address 0FFFFh. Be sure to note microprocssor five hex digits are required to represent a memory address.

Ad is the only way we earn a little money to run this blog domain fees, time for managing and posting contents etc. The physical address is 20 bits long and corresponds to the actual binary code output by the BIU on the address bus micro;rocessor.

Execution unit receives program instruction codes and data from the BIU, executes them and stores. So that the EU gets the instructions for execution in the order they are fetched. This means that slow-memory parts can be used without affecting overall system performance. Once inside the BIU, the instruction is passed to the queue. Assuming that the queue is initially empty, the EU immediately draws this instruction from the queue and begins execution.

The stack segment registers points to the current stack. If you make use of these memory locations, you risk incompatibility with these future products.

Introduction to 8086 Microprocessor

Bus Interface Unit The main function of this block is to calculate the address of the next instruction. BIU also contain an instruction queue. A logical address gives the displacement from the address base of the segment to the desired location within it, as opposed to its “real” address, which maps directly anywhere into the 1 MB memory space.


Implicit and Explicit sequence Control. It accomplishes this task via the three-bus system architecture previously discussed. This feature is called as Pipelining and this is what makes a powerful processor of that time. This corresponds to the 64K-byte length of the segment. Parity Flag PF – set if parity the number of “1” bits in the low-order byte of the result is even. These can be combined to form a bit register. Pointer and Index registers: The feedback you provide will help us show you more relevant content in the future.

Used with string instructions.

In the beginning the CS: How many address lines are present in an microprocessor? All the data, pointer, index and status registers are of 16 bits. The advantage of this pipelined architecture is that the EU can execute instructions almost continually instead of having to wait for the BIU to fetch a new instruction.

By being able to access individual bytes, these odd-length instructions can be handled. Second, many of the ‘s and ‘s operation codes are single bytes.