datasheet, circuit, data sheet: HITACHI – 4-bit D-type site for Electronic Components and Semiconductors, integrated circuits, diodes. datasheet, pdf, data sheet, datasheet, data sheet, pdf, Hitachi Semiconductor, 4-bit D-type Register (with 3-state Outputs). Quad D-type flip-flop; positive-edge trigger; 3-state. PDF datasheet. OE1, 1 •, 16, Vcc. OE2, 2, 15, MR. Q0, 3, 14, D0. Q1, 4, 13, D1. Q2, 5, 12, D2.

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During 3—state operation, these outputs assume a high— impedance state. When either or both of these controls are high, there is no change in the state of the flip—flops, regardless of any changes at the D or Clock inputs.

The data outputs change state on the positive going edge of the clock. During normal operation of the.

(PDF) 74173 Datasheet download

Enable Controls are low, data at the D inputs are loaded into. Active—low Data Enable Control inputs. Data on these pins, when enabled by the Data—Enable Controls, are entered into the flip—flops on the rising edge of the clock. If either of the 2 input disables are taken to a logic high level, the Q outputs are fed back to the inputs, forcing the flip-flops to remain in the same state. When both controls are.

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During normal operation of the device, the outputs of the D flip—flops appear at these pins. When both controls are low, the device outputs display the data in the flip—flops. Home – IC Supply – Link. Clearing is enabled by taking the clear input to a logic. When either or both of the.

If either 7173 the 2 input disables are taken to a logic high level, the Q outputs are fed back to the inputs. A high level on this pin resets all flip—flops and forces the Q outputs low, if they are not already in high—impedance state. During 3—state operation, these outputs assume a high—.

The outputs are placed in the 3-stage mode when if of the output disable pins are in the logic high level. The 3-state outputs allow the. Home – IC Supply – Link. When either M or N or both is are high the output is disabled to the high-impedance state; however sequential operation of the flip-flops is not affected.

Datasheet, PDF – Alldatasheet

A high level on this pin resets all. The outputs are placed in the 3-stage mode when either of the. When both Data Enable Controls are low, data at iv D inputs are loaded into the flip—flops with the rising edge of the Clock input. The four D type Flip-Flops operate synchronously from a common clock.

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When either or both of the Output Enable Controls are high, the Q outputs of the iic are in the high—impedance state.

NTE – IC-TTL Quad D Flip-Flop w/Three-State Outputs

Data on these pins, when enabled by the. Output Enable Control inputs. Clearing is enabled by taking datazheet clear input to a logic high level.

When either M or N or both is are high the output is disabled to the high-impedance state. Data—Enable Controls, are entered into the flip—flops on the. Output Enable Controls are high, the Q outputs of the device.

The input disable allows the flip-flops to remain in their present states without having to disrupt the clock. Datawheet 3-state outputs allow the device to be used in bus organized systems.