0 – July. 1. Qualification Package. AT89C51ED2. FLASH 8-bit C51 Microcontroller. 64 Kbytes FLASH, 2 Kbytes EEPROM. AT89C51RD2 / AT89C51ED2. AT89C51ED2-SLSUM Microchip Technology / Atmel 8-bit Microcontrollers – MCU 64kB Flash B RAM VV datasheet, inventory, & pricing. AT89C51ED2-SLSIM Microchip Technology / Atmel 8-bit Microcontrollers – MCU 80C31 w/4k datasheet, inventory, & pricing.

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Set by user for general purpose usage. Flow Description Overview An initialization step must be performed after each Reset. Generate an enabled external Keyboard interrupt same behavior as external interrupt. Cleared to select 6 clock periods per peripheral clock cycle. This is achieved by applying an internal reset to them.

Page 74 Table To communicate with slave A only, the master must send an address where bit 0 is clear e. Timer 2 operation is similar to Timer 0 and Timer 1. This is the power supply voltage for normal, idle and power-down operation P0.

Output pulse for latching the low byte of the address during an access to external memory. Do not set this bit. Once the internal supply after the voltage regulator reach a safety level, the power monitor then looks at the XTAL clock input.


Don’t see a manual you are looking for? If the program counter ever goes astray, a match will eventually occur and cause an internal reset.

Nevertheless, during internal code execution, ALE signal is still generated. Set by hardware when an invalid stop bit is detected. Tell us what’s missing.

A default serial loader bootloader program allows ISP of the Flash. It is driven by the Master for eight clock cycles which allows to exchange one Byte on the serial lines.

AT89C51ED2 – Microcontrollers and Processors – Microcontrollers and Processors

Page 6 Table Must be cleared by software. Document Revision History Set by hardware to indicate that the SS pin is at inappropriate logic level. Setting TR2 allows TL2 to increment by the selected input. To communicate with slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both at89c51ex2 e. Its advantages include reduced software overhead and improved accuracy.

Watchdog timers are useful for systems that are susceptible to at89c51eed2, power glitches, or electrostatic discharge. Ordering Information Table Security level 2 and 3 should only be programmed after Flash verification.


Page 98 Figure Hardware conditions or regular boot process. Page 56 Table Note that one ALE pulse is skipped during each access to external data memory. Set to select 12 clock periods per peripheral clock cycle. Page 76 Table It is possible to use Timer 2 as a baud rate generator and a clock datassheet simultaneously. The second option is also not recommended if other PCA modules are being used.

Oscillator To optimize the power consumption and execution time needed for a specific task, an internal prescaler feature has been implemented between the oscillator and the CPU and peripherals.

A warm start reset occurs while VCC is still applied to the device and could be generated for example by an exit from power-down. These inputs are available as alternate function of P1 and allow to exit from idle and power-down modes.